Multicarrier, multimode cellular receivers.

Standard serial port interface (SPI) supports various product features and functions, such as data formatting (offset binary, twos complement, or Gray coding), enabling the clock DCS.

Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of input clock pulse widths.

Packaged in a Pb-free, 72-lead LFCSP package.

Ease of use: on-chip reference, high input impedance buffer, adjustable analog input range, and an output clock to simplify data capture.

Outstanding SFDR performance for IF sampling applications such as multicarrier, multimode 3G, and 4G cellular base station receivers.

IF optimization capability used to improve SFDR.

The AD9467 is available in a Pb-free, 72-lead, LFCSP specified over the −40☌ to +85☌ industrial temperature range. Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data test patterns. The internal power-down feature supported via the SPI and typically consumes less than 5 mW when disabled. Data outputs are LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances.Ī data clock output (DCO) for capturing data on the output is provided for signaling a new output bit. No external reference or driver components are required for many applications. The ADC requires 1.8 V and 3.3 V power supplies and a low voltage differential input clock for full performance operation.

The product operates at a 250 MSPS conversion rate and is designed for wireless receivers, instrumentation, and test equipment that require a high dynamic range. It is optimized for high performance over wide bandwidths and ease of use.

The AD9467 is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC).

Analog to digital converter data sheet